Configurable interface circuit

ABSTRACT

A configurable interface circuit is disclosed. An integrated circuit (IC) having a particular configuration. The IC includes a memory system and a communication fabric coupled to the memory system. The IC further includes a plurality of agent circuits configured to make requests to the memory system that are in a first format that is not specific to the particular configuration of the IC. A plurality of interface circuits is coupled between corresponding ones of the plurality of agent circuits and the communication fabric. A given one of the plurality of interface circuits is configured to receive a request to the memory system in the first format and output the request in a second format that is specific to the particular configuration of the IC.

BACKGROUND Technical Field

This disclosure is directed to computer systems, and more particularly,to interface circuits for coupling different functional circuits of acomputer system to one another.

Description of the Related Art

A single computer architecture may have a number of differentimplementations. The various implementations may include commoncircuits, such as memory controllers, cache memories and correspondingcontrollers, processor cores, and so on. The number of these differentcircuits may vary from one implementation of an architecture to another.To facilitate communications among the various functional circuits indifferent implementations thereof, custom interface circuitry may beprovided for the different implementations of the computer architecture.

SUMMARY

A configurable interface circuit is disclosed. In one embodiment, anintegrated circuit (IC) having a particular configuration. The ICincludes a memory system and a communication fabric coupled to thememory system. The IC further includes a plurality of agent circuitsconfigured to make requests to the memory system that are in a firstformat that is not specific to the particular configuration of the IC. Aplurality of interface circuits is coupled between corresponding ones ofthe plurality of agent circuits and the communication fabric. A givenone of the plurality of interface circuits is configured to receive arequest to the memory system in the first format and output the requestin a second format that is specific to the particular configuration ofthe IC.

In various embodiments, the plurality of interface circuits is coupledbetween corresponding ones of the plurality of agent circuits and one ormore components (e.g., such as a communication fabric or other type ofcommunication network). For a given agent circuit, a corresponding giveninterface circuit is configured to present an interface to the memorysystem via the one or more components that is transparent with respectto the interface requirements of the one or more components.

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description makes reference to the accompanyingdrawings, which are now briefly described.

FIG. 1 is a block diagram of one embodiment of an integrated circuit(IC).

FIG. 2 is a block diagram illustrating two differentconfigurations/embodiments of an of an IC utilizing interface circuitscoupled between various agent circuits and a communication fabric.

FIG. 3 is a block diagram of another embodiment of an IC.

FIG. 4 is a block diagram illustrating additional details of anembodiment of an IC.

FIG. 5 is a block diagram illustrating a sequence of communicationsbetween an agent circuit and one or more cache subsystems, via aninterface circuit, in one embodiment of an IC.

FIG. 6 is a flow diagram illustrating one embodiment of a method foroperating an IC.

FIG. 7 is a flow diagram illustrating another embodiment of a method foroperating an IC.

FIG. 8 is a block diagram of one embodiment of an example system.

DETAILED DESCRIPTION OF EMBODIMENTS

The present disclosure is directed to various embodiments of an IC thatutilizes interface circuits between various agent circuits and othercomponents thereon. Many IC families, such as a family ofsystems-on-a-chip (SoCs) have a number of possible configurations thatmay implement/enable different numbers of components thereon. Forexample, a family of SoCs may include a number of differentconfigurations that includes, with respect to one another, differentnumbers of memory controllers, different numbers of cache controllersand corresponding cache memories, and so on. These configurations mayalso include a number of different agent circuits, such as processorcores, peripheral devices, and so on. Communication between the agentcircuits and the memory controller, cache controllers, and so on, may beconducted through various components of, e.g., a communication fabric.Due to the fact that there are different configurations of the SoC, thetopology of the fabric (and the IC overall) is different from oneimplementation to the next.

Communication between the various agent circuits and, e.g., the memorycontrollers via the communication fabric requires facilitation byinterface circuitry. This interface circuitry is typically associatedwith the agent circuits. However, custom designing interface circuitryfor each different configuration of an IC is a burdensome task,particularly if the designs of the agent circuits are to be used fromone embodiment to the next.

Using the recognition of this problem as an insight, the presentdisclosure contemplates a configurable interface circuit. Instances ofthe configurable interface circuit may be coupled between variousinstances of the agent circuits. A given one of the configurableinterface circuits may thus facilitate communications between the agentcircuits and other components of the IC/SoC, e.g., between and agentcircuit and a memory controller via a communication fabric. Theconfigurable interface circuit may have a common design that is re-usedfor the various different implementations of the IC/SoC. For example,the same design of a configurable interface circuit may be instantiatedon a first SoC having two memory controllers and on a second SoC havingfour memory controllers. The configurable interface circuit may, duringa system startup, receive/determine details of the chip topology for theparticular configuration of the IC. Using this information, theconfigurable interface circuit may be configure itself in such a mannerto operate in the corresponding chip configuration. Communicationsbetween a particular agent circuit and other components of the IC/SoCmay be conducted via a correspondingly coupled configurable interfacecircuit.

Using the configurable interface circuit may obviate the need to designcustom interface logic to enable various agent circuits to be used indifferent topologies/configurations of an IC/SoC. Instead, both a commondesign of a particular agent circuit, along with a common design of theconfigurable interface circuit, may be used in different variations ofan IC/SoC, irrespective of the different topologies. This may result ina significant simplification in designing different implementations ofthe IC/SoC. As an added benefit, the configurable interface circuit maybe used to increase security by controlling an amount ofaccess/bandwidth to other components of the IC/SoC that may be obtainedby a particular agent circuit. Similarly, the configurable interfacecircuit may also control access to its respective agent circuit, and maythus provide increased security in this manner as well.

The present disclosure begins with a discussion of a block diagram toprovide a basic description of a configurable interface. Additionalblock diagrams are then provided to enable description of features andoperation of different embodiments of a configurable interface. Methodsfor operating an IC/SoC having at least one instance of a configurableinterface implemented thereon are then discussed in conjunction withcorresponding flow diagrams. The specification then concludes with adescription of an example system in which a configurable interface maybe implemented.

Integrated Circuit with Configurable Interface:

FIG. 1 is a block diagram of an IC having instances of a configurableinterface circuit coupled between corresponding ones of the plurality ofagent circuits and other components of the IC. In the embodiment shown,IC 100 is arranged in a particular configuration, and includes a memorysystem 112 and a communication fabric 110 coupled to memory system 112.IC 100 also includes a plurality of agent circuits 101, ones of whichare configured to make requests to memory system 112 that are in a firstformat that is not specific to the particular configuration of IC 100. Aplurality of interface circuits 105 are coupled between correspondingones of the plurality of agent circuits 101 and communication fabric110. A given one of the plurality of interface circuits 105 isconfigured to receive a request, from its respective agent circuit 101,to the memory system 112 in the first format and output the request in asecond format that is specific to the particular configuration of the IC100.

Generally speaking, each of the interface circuits 105 is configured tofacilitate communications between correspondingly coupled ones of theagent circuits 101 initiated in formats, protocols, etc., that are notspecific to the configuration of IC 100. The interface circuits 105 maytranslate and convey commands/requests to other components on IC 100according to formats, protocols, etc., that are configuration specific.In doing so, the configurable interface circuits 105 present, for thecorrespondingly coupled agent circuits 101, an interface to theremainder of IC 100 that is transparent with respect to the interfacerequirements of, e.g., communication fabric 110 and other components onIC 100. This arrangement allows a particular design of an agent circuit101 to be used in a number of different configurations of an IC. Forexample, use of the interface circuits 105 may allow a common design ofa particular agent circuit to be instantiated in different versions of ascalable computer architecture or on variations of a particular SoC. Thedifferent versions of a particular IC/SoC upon which the agent circuits101 may be instantiated may include different numbers of particularcomponents (e.g., memory controllers, cache controllers, peripheralinterfaces, etc.) with which an agent circuit 101 may conductcommunications. However, due to the presence of the interface circuits105, the need to provide a custom logic design in an agent circuit 101to enable communications with these different numbers of components maybe obviated.

The configurable interface circuits 105 may, in one embodiment, beconfigured during a system startup. Various mechanisms may be used inconfiguring these circuits. For example, in one embodiment, configurableinterface circuits 105 may transmit one or more queries intocommunication fabric 110 and receive responses from other componentscoupled thereto (including other configurable interface circuits 105),storing the responses as configuration information in, e.g., registers.In another embodiment, a system BIOS (Basic Input Output System) maybroadcast configuration information to the various components of IC 100,including the configurable interface circuits 105. Generally speaking,any suitable mechanism which provides IC-specific information to theconfigurable interface circuits 105 may be used in configuring themduring the startup of the system that includes IC 100.

The various agent circuits 101 may be any of a number of different typesof functional circuit units. For example, an agent circuit 101 may be aprocessor core or one of a number of processor cores on a multi-coreprocessor/SoC (with the cores being heterogenous or homogenous),co-processor units, graphics processing units (GPUs) or individual coresthereof, and so on. The communication fabric 110 may include varioustypes of components and links for facilitating on-chip communications.For example, embodiments of communication fabric 110 may include anumber of point-to-point communication links, buses, crossbar switches,and/or other on-chip networking circuitry.

It is noted that many of the communications disclosed herein arediscussed in terms of requests. However, the communications that areconveyed via ones of the configurable interface circuits 105 may beconsidered as one of a number of different types, including commands,queries, and so on. Furthermore, the terms “command” and “request” maybe interchangeable in some instances. For example, the term “writecommand” could be used interchangeably with the term “write request,” asboth of these types of communications indicate that information is to bewritten to some location.

Various IC Configurations with Configurable Interface Circuits:

FIG. 2 is a block diagram illustrating the used of one embodiment of aconfigurable interface circuit in different configurations of an IC. Itis noted that these figures are provided for illustrative purposes, butare not intended to be limiting. Accordingly, the number of interfacecircuits, agent circuits, and other components included on theillustrated may be different than those shown here.

In Configuration #1, an example of an agent circuit 201 and acorresponding configurable interface circuit 205 are shown as beingcoupled to the communication fabric 210. The communication fabric 210 inthis embodiment may have a first topology, Topology #1. The topology ofcommunication fabric 210 may include, for example, a particular numberof point-to-point links, switches, and/or other components used toimplement an on-chip network.

The example of Configuration #1 also includes two memory cachecontrollers 221. Accordingly, interface circuit 205 is configured tofacilitate communications between agent circuit 201 and the twoinstances of memory cache controller 221 in Configuration #1. The numberof memory cache controllers 221, as well as the details of Topology #1of Communication fabric 210 may be received by interface circuit 205during a system startup, via one of the mechanisms discussed above.Other components that are not explicitly shown in FIG. 2 may also beimplemented in Configuration #1. Similarly, the number of agent circuits201 and correspondingly coupled interface circuits 205 may also bepresent despite not being explicitly shown here.

The example of Configuration #2 as illustrated in FIG. 2 includes aninstance of an agent circuit 201 and corresponding interface circuit205. Four instances of a memory cache controller 221 are also present.The communication fabric 251 in this embodiment is arranged in Topology#2, which is different from Topology #1. Accordingly, the number ofcomponents used to implement these respective topologies may bedifferent from one another. It is also possible that one topology mayinclude some components not included in the other. Similarly, the numberof memory cache controllers 221 in the two illustrated configurationsare different from one another, as may be true for other components thatare not shown.

Despite the differences between Configurations #1 and #2, agent circuit201 and interface circuit 205 may be the same design in both. Thus,while interface circuit 205 may be self-configuring usingconfiguration/topology information received during a system startup, thedesign may be the same in both Configuration #1 and Configuration #2.Accordingly, a common design of configurable interface circuit 205 maybe adapted to a number of different configurations. This in turn mayallow a single, non-configuration specific design of agent circuit 201to be used in different versions of an IC (with different topologies)without the need for custom-designed interface logic. Similarly, thesame design of the configurable interface circuits 205 may be used inICs with different topologies, with the various instances thereof beingadapted to the particular IC configuration during a system startuproutine using any suitable mechanism, including ones of the variousmechanisms discussed herein.

FIG. 3 is a block diagram of another embodiment of an IC having a numberof agent circuits and corresponding configurable interface circuits. Inthe embodiment shown, IC 300 is an SoC that includes a number of agentcircuits 301, which may be ones of a number of different types of agentcircuits, such as processor cores. It is noted that individual instancesof the agent circuits 301 may be different from one another and may thusprovide different types of functionality. However, the variousinstances/types of the agent circuits may have a common design that canbe re-used over a number of different IC configurations/topologies whenimplemented in conjunction with a corresponding instance of aconfigurable interface 305.

The configurable interface circuits 305 in the illustrated embodimentare interposed between a corresponding agent circuit 301 andcommunication fabric 310. The communication fabric 310, in turn, isinterposed between the interface circuits 305 and memory system 312. Aswith the other embodiments disclosed herein, communication fabric 310may include various components suitable for realizing an on-chipnetwork, and may be used to carry out communications between on-chipcomponents using suitable protocols.

Memory system 312 in the embodiment shown includes a number of memorycontrollers 313 and corresponding memories 314. In some embodiments, thememories 314 may be part of a larger, contiguous memory having acorresponding contiguous range of physical addresses. Other embodimentsare possible and contemplated in which the memories 314 are separateentities each having their own respective range of physical addresses.

The number of memory controllers 313 and arrangement of memory system312 overall in the embodiment shown is not specifically visible to thevarious ones of agent circuits 301 due to their non-configurationspecific design. Accordingly, when submitting a read or write request toa memory 314 in memory system 312, agent circuit 301 provides therequest in a first, non-configuration specific format (with respect tothe configuration of IC 300) to its correspondingly coupled configurableinterface circuit 305. Upon receiving the request as initially submittedby its respective agent 301, interface circuit 305 transmits the requestto memory system 312 in a second format that is specific to theconfiguration of IC 300.

In a similar manner, a configurable interface circuit 305 may facilitatecommunications with other ones of the components of IC 300. For example,a given agent circuit 301 may at times exchange information with otherones of the agent circuits 301 (which, as noted above, can be differenttypes of functional circuits). These communications may be initiated bya particular one of agent circuits 301 in a first format not specific tothe configuration of IC 300. The communications may be conveyed into thecommunication fabric 310, in a second, configuration-specific format bya corresponding configurable interface circuit 305. Ones of the otherconfigurable interface circuits 305 may receive the communications inthe second format, and convey it back to their respective agent circuits301 in the first format.

As an illustrative example, consider an embodiment of IC 300 in which aparticular agent 301 is a processor core having a local data cache. Inorder to maintain coherency of the data across multiple processor coresand within the memory system, the agent 301 may initiate a snoop todetermine if a particular cache line is stored in other caches or hasbeen written back to memory recently. However, due itsnon-configuration-specific design, the agent circuit 301 initiating thesnoop does not have any specific visibility to the other agent circuits301 and to, e.g., the various memory controllers 313 of memory system312. Accordingly, the initiating agent circuit 301 may submit the snooprequest to its respective configurable interface circuit 305 in a firstformat not specific to the configuration of IC 300. Since the respectiveconfigurable interface circuit 305 does have visibility to the othercomponents implemented on IC 300, it may submit the snoop request in asecond, configuration-specific format. Submitting the snoop request inthe configuration-specific format may include providing information asto which ones of the other agents (e.g., other processor cores withlocal caches) are to receive the snoop request, as well as any cachecontrollers (not shown in this figure) and memory controllers thatshould also receive the request. In response to the snoop request, thevarious receiving components of IC 300 may respond, in the secondformat, to the interface circuit 305 from which it was received.Thereafter, the given interface circuit 305 may provide results of thesnoop request to its respective agent circuit 301 in the first format.

It is noted that, since the second format is configuration-specific andsince the configurable interface circuits 305 have visibility to theother components of the system, communications such as the snoop requestmay be tailored to be received only by pertinent system components.Thus, while another processor core and/or a cache request may receivecommunications such as a snoop request, other components of IC 300 towhich a snoop request is not pertinent (e.g., a peripheral interface)may not be a recipient. This may help optimize the use of availableon-chip communication bandwidth in IC 300. More generally, a giveninstance of a configurable interface circuit per the present disclosuremay control an amount of bandwidth consumed by its corresponding agentcircuit, e.g., by controlling the amount of access it has to a memorysystem, and so on.

FIG. 4 is a block diagram illustrating additional details of anembodiment of an IC with respect to the configurable interface circuits.More particularly, FIG. 4 illustrates a portion of an IC 400 tohighlight additional aspects of the various implementations of aconfigurable interface circuit.

In the embodiment shown, agent circuit 401 is coupled to configurableinterface circuit 405, which includes registers 406 and interface logiccircuit 407. Registers 406 in the embodiment shown may be implemented asa register file that stores various types of information, temporary andpersistent, concerning the operations of IC 400. Information stored inregisters 406 may include system configuration information, such as thenumbers and types of other components on IC 400, topology of an on-chipcommunication network such as communication fabric 410, detailsregarding particular components (e.g., a range of physical memoryaddresses for a particular random access memory), and so on.Communications protocol information may also be stored in ones ofregisters 406 to facilitate communications with other components of IC400. This configuration-specific information may be written into theappropriate ones of registers 406 during a system startup routine, andmay be stored therein as long as the interface circuit 405 is operating.Embodiments are also possible and contemplated where some non-volatilestorage is provided to store system information of the type discussedabove.

Registers 406 may also include registers for providing temporary storageof information pertaining to communications between agent circuit 401and other portions of IC 400. For example, when submitting a request orcommand to to memory, information indicating the particulars of therequest/command may be written into certain ones of registers 406, andthese particulars may include information that is not specific to theconfiguration of IC 400. This information may be temporarily storedtherein until, e.g., such time that the request is conveyed throughcommunication fabric 410 to the intended recipient(s). Upon receiving aresponse to a request, information may be written into various ones ofregisters 406, minus any information specific to the configuration of IC400. The information may then be conveyed from the corresponding ones ofregisters 406, in either a push operation or a pull operation, to agentcircuit 401.

Configurable interface circuit 405 also includes interface logic circuit407, which is coupled to both registers 405 and agent circuit 401. Theinterface logic circuit 407 may carry out various functions, such astranslating communications between the variousnon-configuration-specific and configuration-specific formats. Inperforming such translations, interface logic may access various ones ofregisters 406 that store information indicating the particularconfiguration of IC 400. This may enable interface logic 407 to indicatewhich components of IC 400 are to receive a particular communicationinitiated by agent circuit 401 and thus to avoid unnecessarily consumingbandwidth and resources of communication fabric 410 to broadcastinformation to components of IC 400 that are not intended to be a partyof a particular exchange of information.

Interface logic 407 may also communicate directly with the respectiveagent circuit 401 to carry out various functions. For example, if arequest to read a particular cache line from a cache controller wasrequested, interface logic 407 may provide an indication to agentcircuit 401 that the cache line has been obtained and its contents arestored in appropriate ones of registers 406. Agent circuit 401 may thenretrieve the cache line. Alternatively (and continuing the cache lineexample), embodiments are possible and contemplated wherein interfacecircuit 407 may push the requested cache line directly to agent circuit401.

IC 400 in the embodiment shown includes a cache subsystem 419, whichincludes a memory cache controller 421 and a cache memory 424. The cachesubsystem 419 may be part of a larger memory hierarchy/systemimplemented on IC 400. The cache memory 424 may be any suitable type ofcache memory, and may implement various mapping schemes such asset-associative mapping or fully associative mapping. Memory cachecontroller 421 may perform various control functions related to themanagement of cache memory 424. These functions include readinginformation from cache 424, writing information to cache 424, evictingcache lines, marking cache lines as modified (dirty), invalidating cachelines, and so on.

Memory cache controller 421 in the embodiment shown includes registers422, which, among other functions, provide temporary storage for use incommunications with various ones of the interface circuits 405 that maybe implemented on IC 400. For example, if agent circuit 401 submits acache access request by writing information into registers 406,configurable interface circuit 405 may convey the request by causinginformation to be written into registers 422. Memory cache controller421 may then carry out the request based on the information written intoregisters 422 in response to the conveying of the request fromconfigurable interface circuit 405.

In some embodiments, memory cache controller 421 may enable a portion ofcache memory 424 to be allocated as a temporary random access memory(RAM) buffer 429 for use by (and in response to a request by) a givenone of the configurable interface circuits 405. This may be accomplishedby memory cache controller 421 taking one or more cache lines out oftheir normal use and allocating them for use as the temporary RAM buffer429 by binding them to a particular range of addresses (e.g., programmedI/O [PIO] addresses). The buffer may then be accessed for reads andwrites by the corresponding configurable interface circuit 405 thatinitiated the request. Use of a portion of cache memory 424 as atemporary RAM buffer 429 may be particularly useful when an exchangeinvolving a configurable interface circuit 405 includes moving asignificant amount of data. After the cache space consumed by temporaryRAM buffer 429 is no longer needed, memory cache controller 421 maydeallocate the corresponding cache lines from their use as a buffer byremoving the address bindings.

It is noted that at least some operations described above with referenceto cache subsystem 419 may be similarly carried out in a memory systemand with corresponding memory controllers. Thus, a memory controller asdefined herein may also include registers having a role similar to thoseof registers 422 in the embodiment of FIG. 4 . It is further noted thata memory system as described herein may encompass one or more cachesubsystems while also recognizing the distinct roles of cache memory andsystem memory.

FIG. 5 is a block diagram illustrating a sequence of communicationsbetween an agent circuit and one or more cache subsystems, via aninterface circuit, in one embodiment of an IC. In the illustratedembodiment, IC 500 includes a number of cache subsystems 519, each ofwhich includes a memory cache controller 521 and a cache memory 524.Although not shown here, IC 500 may also include an on-chipnetwork/communication fabric comprising one or more components tofacilitate communications between the various components implementedthereon.

The sequence illustrated in FIG. 5 and discussed herein will bedescribed in terms of a request by agent circuit 501. It is noted thatthis is but one type of communication/exchange that may be facilitatedby configurable interface circuit 505, as other types (includingcommunications initiated by components other than agent circuit 501 butdirected thereto) are possible and contemplated.

Agent circuit 501 in the embodiment shown may initiate a request (1) bysubmitting information regarding the request, in a first format, toconfigurable interface circuit 505. This may be accomplished by, e.g.,writing information to registers in interface circuit 505, similar tothe discussion above with respect to FIG. 4 . Configurable interfacecircuit 505 may respond by translating the request into a second formatand sending it to the various ones of the memory cache controllers 521(2). The request may be sent in the second format due to the fact thatagent circuit 501 may lack visibility to other components of IC 500 dueto its non-configuration-specific design. Accordingly, the visibility tothe other system components is provided by configurable interfacecircuit 505, which translates the request accordingly.

The request may be, to use one example, a request for a cache line byagent circuit 501 from a lower level cache that is embodied by thevarious instances of cache 524. Upon receiving the request, the variousones of memory cache controllers 521 may respond by either providing therequested cache line or an indication that the requested cache line wasnot found in its respectively coupled cache 524 (3). Upon receivingresponses from each of the memory cache controllers 521, interfacecircuit 505 may provide an indication to agent circuit 501 that therequest has been carried out (4). This may include, for example,providing the requested cache line, or indicating that the requestedcache line has been received and is stored in registers of interfacecircuit 505 and ready for agent circuit 501. After receiving therequested cache line from interface circuit 505, agent circuit 501 mayprovide an acknowledgement signal to interface circuit 505 (5).

Methods for Operating an IC Having a Configurable Interface:

FIG. 6 is a flow diagram of one embodiment of a method for operating anIC having at least one instance of a configurable interface per thepresent disclosure. Method 600 may be performed with any of the hardwareembodiments discussed above. Hardware embodiments capable of carryingout Method 600 but not otherwise disclosed herein are neverthelessconsidered to fall within the scope of this disclosure.

Method 600 includes initiating, in an agent circuit implemented on anintegrated circuit (IC) having a particular configuration, a request foraccess to a memory of a memory system, wherein the request is in a firstformat that is not specific to the particular configuration of the IC(block 605). The method continues with receiving the request in aninterface circuit coupled between the agent circuit and a communicationfabric coupled to the memory system (block 610). Thereafter, the methodincludes outputting the request, from the interface circuit, in a secondformat that is specific to the particular configuration of the IC,wherein the request is conveyed, through the communication fabric, to atleast one memory controller of the memory system (block 615).

In various embodiments, the method further includes providing, during asystem startup, information regarding the particular configuration tothe interface circuit, wherein providing the information includesspecifying a number of memory controllers within the memory system and atopology of the communication fabric. Receiving information regardingthe particular configuration of the interface circuit may be carried outby various mechanisms. For example, the configurable interface may sendone or more queries to a communication fabric or other on-chipcommunication network and can determine the chip configuration based onthe response received. In another embodiment, a system BIOS maybroadcast configuration information to various circuit units of theIC/SoC, including the configurable interface circuits. Upon receivingconfiguration information, a given configurable interface circuit maystore this information in, e.g., various registers therein, and maytailor its operations accordingly.

In various embodiments of the method, initiating the request comprisesthe agent circuit writing information in the first format to one or moreregisters in the interface circuit. Such embodiments may also includethe interface circuit writing information into one or more memorycontrollers of the memory system in response to the agent circuitwriting information into the one or more registers of the interfacecircuit. Embodiments may also include the interface circuit writinginformation into one or more cache controllers of the memory system inresponse to the agent circuit writing information into the one or moreregisters of the interface circuit.

In some embodiments, the method includes the interface circuitrequesting an allocation of a portion of a cache memory of the memorysystem for use as a random access memory (RAM) buffer. More generally,the configurable interface circuit may communicate with various othercircuit units on the IC/SoC including memory controllers and cachecontrollers within a memory subsystem. Communications may be conductedthrough a communications fabric, bussed communications system, or anyother suitable mechanism that facilitates communications between variouscircuit units on the IC/SoC.

FIG. 7 is a flow diagram of another embodiment of a method for operatingan IC/SoC having a configurable interface circuit. As with Method 600discussed above, Method 700 may be performed using any of the varioushardware embodiments discussed herein. Hardware embodiments notexplicitly discussed herein but having the capability of carrying outMethod 700 are considered to fall within the scope of this disclosure.

Method 700 includes receiving, in ones of a plurality of interfacecircuits of an integrated circuit (IC) during a system startup,information indicative of a corresponding topology of the IC, theintegrated circuit including one or more components interposed between aplurality of agent circuits and a memory system, the one or morecomponents having interface requirements that vary across differentconfigurations of the IC (block 705). The method further includesinitiating, in one of the plurality of agent circuits, a request to amemory system, wherein initiating the request comprises the one of theplurality of agents communicating with a corresponding one of aplurality of interface circuits (block 710). Thereafter, the methodincludes causing operations to be performed in the memory system usingthe one of the plurality of interface circuits and via the one or morecomponents interposed between the plurality of agent circuits and thememory system (block 715). After the request is carried out, the methodincludes determining, by the one of the plurality of interface circuits,that the request has been completed (block 720). In response to thedetermining, the method includes providing an indication to the one ofthe plurality of agents that the request has been completed (block 725).

As noted above, Method 700 may be carried out by a number of differenthardware embodiments. One such embodiment is an IC that includes amemory system and a plurality of agent circuits configured to makerequests to the memory system. The system also includes one or morecomponents interposed between the plurality of agent circuits and thememory system, wherein the one of more components have interfacerequirements that vary across different configurations of the IC. Aplurality of interface circuits is coupled between corresponding ones ofthe plurality of agent circuits and the one or more components, whereinfor a given agent circuit, a corresponding given interface circuit isconfigured to present an interface to the memory system via the one ormore components that is transparent with respect to the interfacerequirements of the one or more components. Other hardware embodimentscapable of carrying out method 700 are also possible and contemplated.

Example System:

Turning next to FIG. 8 , a block diagram of one embodiment of a system800 is shown that may incorporate and/or otherwise utilize the methodsand mechanisms described herein. In the illustrated embodiment, thesystem 800 includes at least one instance of a system on chip (SoC) 806which may include multiple types of processing units, such as a centralprocessing unit (CPU), a graphics processing unit (GPU), or otherwise, acommunication fabric, and interfaces to memories and input/outputdevices. In some embodiments, one or more processors in SoC 806 includemultiple execution lanes and an instruction issue queue. In variousembodiments, SoC 806 is coupled to external memory 802, peripherals 804,and power supply 808.

In various embodiments, SoC 806 may include instances of a configurableinterface as discussed above. SoC 806 may be instantiated in variousdifferent configurations, with different types of communicationnetworks/fabrics, different numbers of memory controllers, cachecontrollers, and so on. More generally, different versions of SoC 806may have correspondingly different topologies. Nevertheless, a commondesign of a configurable interface as disclosed herein may beinstantiated along with various agent circuits. This in turn may obviatethe need to design different interface logic to facilitatecommunications between the various agent circuits and other componentsof SoC 806. The configurable interface circuits may be self-configuringin the manner described above, e.g., during a system startup routine.

A power supply 808 is also provided which supplies the supply voltagesto SoC 806 as well as one or more supply voltages to the memory 802and/or the peripherals 804. In various embodiments, power supply 808represents a battery (e.g., a rechargeable battery in a smart phone,laptop or tablet computer, or other device). In some embodiments, morethan one instance of SoC 806 is included (and more than one externalmemory 802 is included as well).

The memory 802 is any type of memory, such as dynamic random accessmemory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2,DDR3, etc.) SDRAM (including mobile versions of the SDRAMs such asmDDR3, etc., and/or low power versions of the SDRAMs such as LPDDR2,etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memorydevices are coupled onto a circuit board to form memory modules such assingle inline memory modules (SIMMs), dual inline memory modules(DIMMs), etc. Alternatively, the devices are mounted with a SoC or anintegrated circuit in a chip-on-chip configuration, a package-on-packageconfiguration, or a multi-chip module configuration.

The peripherals 804 include any desired circuitry, depending on the typeof system 800. For example, in one embodiment, peripherals 804 includesdevices for various types of wireless communication, such as Wi-Fi,Bluetooth, cellular, global positioning system, etc. In someembodiments, the peripherals 804 also include additional storage,including RAM storage, solid state storage, or disk storage. Theperipherals 804 include user interface devices such as a display screen,including touch display screens or multitouch display screens, keyboardor other input devices, microphones, speakers, etc.

As illustrated, system 800 is shown to have application in a wide rangeof areas. For example, system 800 may be utilized as part of the chips,circuitry, components, etc., of a desktop computer 810, laptop computer820, tablet computer 830, cellular or mobile phone 840, or television850 (or set-top box coupled to a television). Also illustrated is asmartwatch and health monitoring device 860. In some embodiments,smartwatch 860 may include a variety of general-purpose computingrelated functions. For example, a smartwatch may provide access toemail, cellphone service, a user calendar, and so on. In variousembodiments, a health monitoring device may be a dedicated medicaldevice or otherwise include dedicated health related functionality. Forexample, a health monitoring device may monitor a user's vital signs,track proximity of a user to other users for the purpose ofepidemiological social distancing, contact tracing, providecommunication to an emergency service in the event of a health crisis,and so on. In various embodiments, the above-mentioned smartwatch may ormay not include some or any health monitoring related functions. Otherwearable devices are contemplated as well, such as devices worn aroundthe neck, devices that are implantable in the human body, glassesdesigned to provide an augmented and/or virtual reality experience, andso on.

System 800 may further be used as part of a cloud-based service(s) 870.For example, the previously mentioned devices, and/or other devices, mayaccess computing resources in the cloud (i.e., remotely located hardwareand/or software resources). Still further, system 800 may be utilized inone or more devices of a home other than those previously mentioned. Forexample, appliances within the home may monitor and detect conditionsthat warrant attention. For example, various devices within the home(e.g., a refrigerator, a cooling system, etc.) may monitor the status ofthe device and provide an alert to the homeowner (or, for example, arepair facility) should a particular event be detected. Alternatively, athermostat may monitor the temperature in the home and may automateadjustments to a heating/cooling system based on a history of responsesto various conditions by the homeowner. Also illustrated in FIG. 8 isthe application of system 800 to various modes of transportation. Forexample, system 800 may be used in the control and/or entertainmentsystems of aircraft, trains, buses, cars for hire, private automobiles,waterborne vessels from private boats to cruise liners, scooters (forrent or owned), and so on. In various cases, system 800 may be used toprovide automated guidance (e.g., self-driving vehicles), generalsystems control, and otherwise. These any many other embodiments arepossible and are contemplated. It is noted that the devices andapplications illustrated in FIG. 8 are illustrative only and are notintended to be limiting. Other devices are possible and arecontemplated.

The present disclosure includes references to “an “embodiment” or groupsof “embodiments” (e.g., “some embodiments” or “various embodiments”).Embodiments are different implementations or instances of the disclosedconcepts. References to “an embodiment,” “one embodiment,” “a particularembodiment,” and the like do not necessarily refer to the sameembodiment. A large number of possible embodiments are contemplated,including those specifically disclosed, as well as modifications oralternatives that fall within the spirit or scope of the disclosure.

This disclosure may discuss potential advantages that may arise from thedisclosed embodiments. Not all implementations of these embodiments willnecessarily manifest any or all of the potential advantages. Whether anadvantage is realized for a particular implementation depends on manyfactors, some of which are outside the scope of this disclosure. Infact, there are a number of reasons why an implementation that fallswithin the scope of the claims might not exhibit some or all of anydisclosed advantages. For example, a particular implementation mightinclude other circuitry outside the scope of the disclosure that, inconjunction with one of the disclosed embodiments, negates or diminishesone or more the disclosed advantages. Furthermore, suboptimal designexecution of a particular implementation (e.g., implementationtechniques or tools) could also negate or diminish disclosed advantages.Even assuming a skilled implementation, realization of advantages maystill depend upon other factors such as the environmental circumstancesin which the implementation is deployed. For example, inputs supplied toa particular implementation may prevent one or more problems addressedin this disclosure from arising on a particular occasion, with theresult that the benefit of its solution may not be realized. Given theexistence of possible factors external to this disclosure, it isexpressly intended that any potential advantages described herein arenot to be construed as claim limitations that must be met to demonstrateinfringement. Rather, identification of such potential advantages isintended to illustrate the type(s) of improvement available to designershaving the benefit of this disclosure. That such advantages aredescribed permissively (e.g., stating that a particular advantage “mayarise”) is not intended to convey doubt about whether such advantagescan in fact be realized, but rather to recognize the technical realitythat realization of such advantages often depends on additional factors.

Unless stated otherwise, embodiments are non-limiting. That is, thedisclosed embodiments are not intended to limit the scope of claims thatare drafted based on this disclosure, even where only a single exampleis described with respect to a particular feature. The disclosedembodiments are intended to be illustrative rather than restrictive,absent any statements in the disclosure to the contrary. The applicationis thus intended to permit claims covering disclosed embodiments, aswell as such alternatives, modifications, and equivalents that would beapparent to a person skilled in the art having the benefit of thisdisclosure.

For example, features in this application may be combined in anysuitable manner. Accordingly, new claims may be formulated duringprosecution of this application (or an application claiming prioritythereto) to any such combination of features. In particular, withreference to the appended claims, features from dependent claims may becombined with those of other dependent claims where appropriate,including claims that depend from other independent claims. Similarly,features from respective independent claims may be combined whereappropriate.

Accordingly, while the appended dependent claims may be drafted suchthat each depends on a single other claim, additional dependencies arealso contemplated. Any combinations of features in the dependent claimsthat are consistent with this disclosure are contemplated and may beclaimed in this or another application. In short, combinations are notlimited to those specifically enumerated in the appended claims.

Where appropriate, it is also contemplated that claims drafted in oneformat or statutory type (e.g., apparatus) are intended to supportcorresponding claims of another format or statutory type (e.g., method).

Because this disclosure is a legal document, various terms and phrasesmay be subject to administrative and judicial interpretation. Publicnotice is hereby given that the following paragraphs, as well asdefinitions provided throughout the disclosure, are to be used indetermining how to interpret claims that are drafted based on thisdisclosure.

References to a singular form of an item (i.e., a noun or noun phrasepreceded by “a,” “an,” or “the”) are, unless context clearly dictatesotherwise, intended to mean “one or more.” Reference to “an item” in aclaim thus does not, without accompanying context, preclude additionalinstances of the item. A “plurality” of items refers to a set of two ormore of the items.

The word “may” is used herein in a permissive sense (i.e., having thepotential to, being able to) and not in a mandatory sense (i.e., must).

The terms “comprising” and “including,” and forms thereof, areopen-ended and mean “including, but not limited to.”

When the term “or” is used in this disclosure with respect to a list ofoptions, it will generally be understood to be used in the inclusivesense unless the context provides otherwise. Thus, a recitation of “x ory” is equivalent to “x or y, or both,” and thus covers 1) x but not y,2) y but not x, and 3) both x and y. On the other hand, a phrase such as“either x or y, but not both” makes clear that “or” is being used in theexclusive sense.

A recitation of “w, x, y, or z, or any combination thereof” or “at leastone of . . . w, x, y, and z” is intended to cover all possibilitiesinvolving a single element up to the total number of elements in theset. For example, given the set [w, x, y, z], these phrasings cover anysingle element of the set (e.g., w but not x, y, or z), any two elements(e.g., w and x, but not y or z), any three elements (e.g., w, x, and y,but not z), and all four elements. The phrase “at least one of . . . w,x, y, and z” thus refers to at least one element of the set [w, x, y,z], thereby covering all possible combinations in this list of elements.This phrase is not to be interpreted to require that there is at leastone instance of w, at least one instance of x, at least one instance ofy, and at least one instance of z.

Various “labels” may precede nouns or noun phrases in this disclosure.Unless context provides otherwise, different labels used for a feature(e.g., “first circuit,” “second circuit,” “particular circuit,” “givencircuit,” etc.) refer to different instances of the feature.Additionally, the labels “first,” “second,” and “third” when applied toa feature do not imply any type of ordering (e.g., spatial, temporal,logical, etc.), unless stated otherwise.

The phrase “based on” is used to describe one or more factors thataffect a determination. This term does not foreclose the possibilitythat additional factors may affect the determination. That is, adetermination may be solely based on specified factors or based on thespecified factors as well as other, unspecified factors. Consider thephrase “determine A based on B.” This phrase specifies that B is afactor that is used to determine A or that affects the determination ofA. This phrase does not foreclose that the determination of A may alsobe based on some other factor, such as C. This phrase is also intendedto cover an embodiment in which A is determined based solely on B. Asused herein, the phrase “based on” is synonymous with the phrase “basedat least in part on.”

The phrases “in response to” and “responsive to” describe one or morefactors that trigger an effect. This phrase does not foreclose thepossibility that additional factors may affect or otherwise trigger theeffect, either jointly with the specified factors or independent fromthe specified factors. That is, an effect may be solely in response tothose factors, or may be in response to the specified factors as well asother, unspecified factors. Consider the phrase “perform A in responseto B.” This phrase specifies that B is a factor that triggers theperformance of A, or that triggers a particular result for A. Thisphrase does not foreclose that performing A may also be in response tosome other factor, such as C. This phrase also does not foreclose thatperforming A may be jointly in response to B and C. This phrase is alsointended to cover an embodiment in which A is performed solely inresponse to B. As used herein, the phrase “responsive to” is synonymouswith the phrase “responsive at least in part to.” Similarly, the phrase“in response to” is synonymous with the phrase “at least in part inresponse to.”

Within this disclosure, different entities (which may variously bereferred to as “units,” “circuits,” other components, etc.) may bedescribed or claimed as “configured” to perform one or more tasks oroperations. This formulation—[entity] configured to [perform one or moretasks]—is used herein to refer to structure (i.e., something physical).More specifically, this formulation is used to indicate that thisstructure is arranged to perform the one or more tasks during operation.A structure can be said to be “configured to” perform some tasks even ifthe structure is not currently being operated. Thus, an entity describedor recited as being “configured to” perform some tasks refers tosomething physical, such as a device, circuit, a system having aprocessor unit and a memory storing program instructions executable toimplement the task, etc. This phrase is not used herein to refer tosomething intangible.

In some cases, various units/circuits/components may be described hereinas performing a set of tasks or operations. It is understood that thoseentities are “configured to” perform those tasks/operations, even if notspecifically noted.

The term “configured to” is not intended to mean “configurable to.” Anunprogrammed FPGA, for example, would not be considered to be“configured to” perform a particular function. This unprogrammed FPGAmay be “configurable to” perform that function, however. Afterappropriate programming, the FPGA may then be said to be “configured to”perform the particular function.

For purposes of United States patent applications based on thisdisclosure, reciting in a claim that a structure is “configured to”perform one or more tasks is expressly intended not to invoke 35 U.S.C.§ 112(f) for that claim element. Should Applicant wish to invoke Section112(f) during prosecution of a United States patent application based onthis disclosure, it will recite claim elements using the “means for”[performing a function] construct.

Different “circuits” may be described in this disclosure. These circuitsor “circuitry” constitute hardware that includes various types ofcircuit elements, such as combinatorial logic, clocked storage devices(e.g., flip-flops, registers, latches, etc.), finite state machines,memory (e.g., random-access memory, embedded dynamic random-accessmemory), programmable logic arrays, and so on. Circuitry may be customdesigned, or taken from standard libraries. In various implementations,circuitry can, as appropriate, include digital components, analogcomponents, or a combination of both. Certain types of circuits may becommonly referred to as “units” (e.g., a decode unit, an arithmeticlogic unit (ALU), functional unit, memory management unit (MMU), etc.).Such units also refer to circuits or circuitry.

The disclosed circuits/units/components and other elements illustratedin the drawings and described herein thus include hardware elements suchas those described in the preceding paragraph. In many instances, theinternal arrangement of hardware elements within a particular circuitmay be specified by describing the function of that circuit. Forexample, a particular “decode unit” may be described as performing thefunction of “processing an opcode of an instruction and routing thatinstruction to one or more of a plurality of functional units,” whichmeans that the decode unit is “configured to” perform this function.This specification of function is sufficient, to those skilled in thecomputer arts, to connote a set of possible structures for the circuit.

In various embodiments, as discussed in the preceding paragraph,circuits, units, and other elements may be defined by the functions oroperations that they are configured to implement. The arrangement andsuch circuits/units/components with respect to each other and the mannerin which they interact form a microarchitectural definition of thehardware that is ultimately manufactured in an integrated circuit orprogrammed into an FPGA to form a physical implementation of themicroarchitectural definition. Thus, the microarchitectural definitionis recognized by those of skill in the art as structure from which manyphysical implementations may be derived, all of which fall into thebroader structure described by the microarchitectural definition. Thatis, a skilled artisan presented with the microarchitectural definitionsupplied in accordance with this disclosure may, without undueexperimentation and with the application of ordinary skill, implementthe structure by coding the description of the circuits/units/componentsin a hardware description language (HDL) such as Verilog or VHDL. TheHDL description is often expressed in a fashion that may appear to befunctional. But to those of skill in the art in this field, this HDLdescription is the manner that is used to transform the structure of acircuit, unit, or component to the next level of implementationaldetail. Such an HDL description may take the form of behavioral code(which is typically not synthesizable), register transfer language (RTL)code (which, in contrast to behavioral code, is typicallysynthesizable), or structural code (e.g., a netlist specifying logicgates and their connectivity). The HDL description may subsequently besynthesized against a library of cells designed for a given integratedcircuit fabrication technology, and may be modified for timing, power,and other reasons to result in a final design database that istransmitted to a foundry to generate masks and ultimately produce theintegrated circuit. Some hardware circuits or portions thereof may alsobe custom-designed in a schematic editor and captured into theintegrated circuit design along with synthesized circuitry. Theintegrated circuits may include transistors and other circuit elements(e.g. passive elements such as capacitors, resistors, inductors, etc.)and interconnect between the transistors and circuit elements. Someembodiments may implement multiple integrated circuits coupled togetherto implement the hardware circuits, and/or discrete elements may be usedin some embodiments. Alternatively, the HDL design may be synthesized toa programmable logic array such as a field programmable gate array(FPGA) and may be implemented in the FPGA. This decoupling between thedesign of a group of circuits and the subsequent low-levelimplementation of these circuits commonly results in the scenario inwhich the circuit or logic designer never specifies a particular set ofstructures for the low-level implementation beyond a description of whatthe circuit is configured to do, as this process is performed at adifferent stage of the circuit implementation process.

The fact that many different low-level combinations of circuit elementsmay be used to implement the same specification of a circuit results ina large number of equivalent structures for that circuit. As noted,these low-level circuit implementations may vary according to changes inthe fabrication technology, the foundry selected to manufacture theintegrated circuit, the library of cells provided for a particularproject, etc. In many cases, the choices made by different design toolsor methodologies to produce these different implementations may bearbitrary.

Moreover, it is common for a single implementation of a particularfunctional specification of a circuit to include, for a givenembodiment, a large number of devices (e.g., millions of transistors).Accordingly, the sheer volume of this information makes it impracticalto provide a full recitation of the low-level structure used toimplement a single embodiment, let alone the vast array of equivalentpossible implementations. For this reason, the present disclosuredescribes structure of circuits using the functional shorthand commonlyemployed in the industry.

Numerous variations and modifications will become apparent to thoseskilled in the art once the above disclosure is fully appreciated. It isintended that the following claims be interpreted to embrace all suchvariations and modifications.

What is claimed is:
 1. An apparatus, comprising: an integrated circuit(IC) having a particular configuration, wherein the IC includes: amemory system; a communication fabric coupled to the memory system; aplurality of agent circuits configured to make requests to the memorysystem that are in a first format that is not specific to the particularconfiguration of the IC; a plurality of interface circuits coupledbetween corresponding ones of the plurality of agent circuits and thecommunication fabric, wherein a given one of the plurality of interfacecircuits is configured to receive a request to the memory system in thefirst format and output the request in a second format that is specificto the particular configuration of the IC; wherein the given one of theplurality of interface circuits includes a corresponding interface logiccircuit and a corresponding register file, wherein the interface logiccircuit is configured to initiate communications with components of thememory system in response to receiving a request from a correspondinglycoupled agent, translate communications between the correspondinglycoupled agent and the memory system between a non-configuration specificformat and a configuration specific format, and to store informationobtained from the request in one or more registers of the register file.2. The apparatus of claim 1, wherein the given one of the plurality ofinterface circuits is configured to receive information indicative ofthe particular configuration of the IC during a startup of theapparatus, and further configured to store the information indicative ofthe particular configuration in one or more registers of the registerfile.
 3. The apparatus of claim 1, wherein the particular configurationspecifies a number of memory controllers within the memory system. 4.The apparatus of claim 1, wherein the particular configuration specifiesa topology of the communication fabric.
 5. The apparatus of claim 1,wherein the given one of the plurality of interface circuits is coupledto a particular one of the plurality of agent circuits, and wherein theparticular one of the plurality of agent circuits is configured toinitiate a memory command in the first format by writing to one or moreregisters of the register file in the given one of the plurality ofinterface circuits.
 6. The apparatus of claim 5, wherein thecorresponding interface logic circuit of the given one of the pluralityof interface circuits is configured to, in response to the particularone of the plurality of agent circuits initiating the memory command,communicate the memory command in a second format to at least one memorycontroller of the memory system by writing to registers in the at leastone memory controller.
 7. The apparatus of claim 1, wherein the givenone of the plurality of interface circuits is configured to control anamount of bandwidth for communication with the memory system for itsrespectively coupled one of the plurality of agent circuits.
 8. Theapparatus of claim 1, wherein the given one of the plurality ofinterface circuits is configured to request allocation of a portion of acache memory of the memory system as a random access memory (RAM) bufferfor a respective one of the plurality of agent circuits.
 9. Theapparatus of claim 1, wherein the memory system includes one or morecache controllers, and wherein the given one of the plurality ofinterface circuits is configured to output the request to one or more ofthe cache controllers.
 10. A method comprising: initiating, in an agentcircuit implemented on an integrated circuit (IC) having a particularconfiguration, a request for access to a memory of a memory system,wherein the request is in a first format that is not specific to theparticular configuration of the IC; receiving the request in aninterface circuit coupled between the agent circuit and a communicationfabric coupled to the memory system; initiating, by an interface logiccircuit in the interface circuit and through the communication fabric,communication with components of the memory system specified in therequest; translating communications, using an interface logic circuit,between the agent circuit and the memory system between anon-configuration specific format and a configuration specific format;storing, in one or more registers of a register file in the interfacecircuit, information obtained from the request; and outputting theinformation obtained from the request, from the interface circuit, in asecond format that is specific to the particular configuration of theIC, wherein the request is conveyed, through the communication fabric,to at least one memory controller of the memory system.
 11. The methodof claim 10, further comprising providing, during a system startup,information regarding the particular configuration to the interfacecircuit, wherein providing the information includes specifying a numberof memory controllers within the memory system and a topology of thecommunication fabric, and wherein the method further comprises storingthe information regarding the particular configuration, in selectedregisters of the register file.
 12. The method of claim 10, whereininitiating the request comprises the agent circuit writing informationin the first format to at least one register in the register file of theinterface circuit.
 13. The method of claim 12, further comprising theinterface logic circuit writing information into one or more memorycontrollers of the memory system in response to the agent circuitwriting information into the at least one register of the register file.14. The method of claim 12, further comprising the interface logiccircuit writing information into one or more cache controllers of thememory system in response to the agent circuit writing information intothe at least one register of the register file.
 15. The method of claim10, further comprising the interface circuit requesting an allocation ofa portion of a cache memory of the memory system for use as a randomaccess memory (RAM) buffer.
 16. An apparatus, comprising: an integratedcircuit (IC), wherein the IC includes: a memory system; a plurality ofagent circuits configured to make requests to the memory system; one ormore components interposed between the plurality of agent circuits andthe memory system, wherein the one of more components have interfacerequirements that vary across different configurations of the IC; and aplurality of interface circuits coupled between corresponding ones ofthe plurality of agent circuits and the one or more components, whereinfor a given agent circuit, a corresponding given interface circuit ofthe plurality of interface circuits is configured to present aninterface to the memory system via the one or more components that istransparent with respect to the interface requirements of the one ormore components; wherein the given interface circuit includes acorresponding interface logic circuit configured to communicate with theone or more components and a correspondingly coupled one of theplurality of agent circuits and to translate communications between thecorrespondingly coupled one of the plurality of agent circuits and thememory system between a non-configuration specific format and aconfiguration specific format; and wherein the given interface circuitfurther includes a register file, wherein the interface logic circuit isconfigured to access, from one or more registers of the register file,protocol information to facilitate communications with the one or morecomponents.
 17. The apparatus of claim 16, wherein the one or morecomponents and the memory system are arranged in a selected topology,wherein the given interface circuit is configured to route requests fromthe given agent circuit to the memory system according to the interfacerequirements of the selected topology in a manner that is transparent tothe given agent circuit.
 18. The apparatus of claim 17, wherein thegiven interface circuit is configured to receive and store, in at leastone register of the register file, information indicative of theselected topology during a system startup, wherein the informationindicative of the selected topology includes a number of memorycontrollers in the memory system.
 19. The apparatus of claim 17, whereinthe one or more components comprise a communication fabric, and whereinthe given interface circuit configured to receive and store, in at leastone register of the register file, during a system startup, informationindicative of a selected topology of the communication fabric.
 20. Theapparatus of claim 16, wherein ones of the plurality of agent circuitsare configured to make requests to the memory system by writing therequests to at least one register in the register file and in a firstformat that is not specific to a particular configuration of the IC, andwherein the interface logic circuit of the given interface circuit isconfigured to convey the requests, to the memory system via the one ormore components in a second format that is specific to the particularconfiguration of the IC.